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? semiconductor components industries, llc, 2009 july, 2009 ? rev. 0 1 publication order number: NCP5217A/d NCP5217A single synchronous step-down controller the NCP5217A is a synchronous step ? down controller for high performance systems battery ? power systems. the NCP5217A includes a high ef ficiency pwm controller. a pin is provided to enable or disable forced pwm mode of operation. an internal power good voltage monitor tracks the smps output. NCP5217A also features soft ? start sequence, uvlo for v cc and switcher, overvoltage protection, overcurrent protection, undervoltage protection and thermal shutdown. the ic is packaged in qfn14. features ? 0.8% accuracy 0.8 v reference ? 4.5 v to 27 v battery/adaptor voltage range ? adjustable output voltage range: 0.8 v to 3.3 v ? selectable power saving mode / force pwm mode ? lossless inductor current sensing ? programmable transient ? response ? enhancement (tre) control ? programmable adaptive voltage positioning (avp) ? input supply feedforward control ? internal soft ? start ? integrated output discharge (soft ? stop) ? build ? in adaptive gate drivers ? pgood indication ? overvoltage, undervoltage and overcurrent protections ? thermal shutdown ? qfn14 package ? these devices are pb ? free and are rohs compliant typical applications ? notebook application ? system power device package shipping ? ordering information NCP5217Amntxg qfn16 (pb ? free) 3000 / tape & reel qfn14 case 485al marking diagram http://onsemi.com a = assembly location l = wafer lot y = year w = work week = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. qfn14 (top view) (note: microdot may be in either location) n5217 alyw 114 2 3 4 5 6 13 12 11 10 9 78 cs+ cs ? /vo comp fb pgood dh swn idrp/ocp vcc dl/treset en_skip bst agnd pgnd
NCP5217A http://onsemi.com 2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 bst dh swn idrp/ocp vcc dl/treset pgnd en_skip cs+ cs ? /vo comp fb pgood agnd idrp/ocp detection control logic, protection, ramp generator and pwm logic over current detector avp control vref + ? + ? disch cdiff uvlo control vcc ? + ? + ? + ? + vref+10% vref ? 10% vref ? 20% vref+15% pgh pgl uvp ovp pgood osc level control enable fpwm skip thermal shutdown error amplifier current sense amplifier NCP5217A oc & tre detection figure 1. block diagram +5v en_skip vin vout pgnd pgood bst dh swn idrp/ocp vcc pgnd agnd pgood cs ? /vo comp fb dl/treset en_skip cs+ 6 NCP5217A 5 4 3 2 7 1 14 8 9 10 11 12 13 qfn14 figure 2. typical application circuit
NCP5217A http://onsemi.com 3 pin function description pin no. symbol description 1 en_skip this pin serves as two functions. enable: logic control for enabling the switcher. skip: power saving mode (skip and force pwm) programmable pin. 2 cs+ inductor current differential sense non ? inverting input. 3 cs ? /vo inductor current differential sense inverting input. 4 comp output of the error amplifier. 5 fb output voltage feed back. 6 pgood power good indicator of the output voltage. high impendence (open drain) if power good (in regulation). low impendence if power not good. 7 agnd analog ground. 8 pgnd ground reference and high ? current return path for the bottom gate driver. 9 dl/treset gate driver output of bottom n ? channel mosfet. it also has the function for treset. 10 vcc supply for analog circuit and bottom gate driver. 11 idrp/ocp over current protection and droop voltage programmable pin. 12 swn switch node between the top mosfet and bottom mosfet. 13 dh gate driver output of the top n ? channel mosfet. 14 bst top gate driver input supply, a bootstrap capacitor connection between swn and this pin. absolute maximum ratings rating symbol value unit vcc power supply voltage to agnd vcc ? 0.3, 6.0 v high ? side gate drive supply: bst to swn high ? side gate drive voltage: dh to swn low ? side gate drive supply: vcc to pgnd low ? side gate drive voltage: dl to pgnd v bst ? v swn, v dh ? v swn, vcc ? v pgnd, v dl ? v pgnd, ? 0.3, 6.0 v input / output pins to agnd v io ? 0.3, 6.0 v switch node swn v swn ? 5 v (< 100 ns) 30 v v high ? side gate drive/low ? side gate drive outputs dh, dl ? 3(dc) v pgnd v pgnd ? 0.3, 0.3 v thermal characteristics thermal resistance junction ? to ? ambient (qfn14 package) r ja_qfn14 48 c/w operating junction temperature range (note 1) t j ? 40 to + 150 c operating ambient temperature range t a ? 40 to + 85 c storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling. 1. internally limited by thermal shutdown, 150 c min.
NCP5217A http://onsemi.com 4 electrical characteristics (v in = 12 v, v cc = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics symbol test conditions min typ max unit supply voltage input voltage v in 4.5 ? 27 v v cc operating voltage v cc 4.5 5.0 5.5 v supply current v cc quiescent supply current in fpwm operation ivcc_fpwm en_skip = 2.0 v, v fb forced above regulation point. dh, dl are open 1.5 2.5 ma v cc quiescent supply current in power saving operation ivcc_ps en_skip = 5 v, v fb forced above regulation point, dh, dl are open 1.5 2.5 ma v cc shutdown current ivcc_sd en_skip = l, v cc = 5 v, true shutdown 1 ua bst quiescent supply current in fpwm operation ibst_fpwm en_skip = 1.5 v, v fb forced above regulation point, dh and dl are open, no boost trap diode 0.3 ma bst quiescent supply current in power ? saving operation ibst_ps en_skip = 5 v, v fb forced above regulation point, dh and dl are open no boost trap diode 0.3 ma bst shutdown current ibst_sd en_skip = 0 v 1 a dv/dt on v cc dvcc/dt (note 2) ? 10 10 v/ s voltage ? monitor rising v cc threshold vccth+ wake up 4.05 4.25 4.48 v v cc uvlo hysteresis vcchys 200 275 400 mv power good high threshold vpgh pgood in from higher vo (pgood goes high) 105 110 115 % power good high hysteresis vpgh_hys pgood high hysteresis (pgood goes low) 5 % power good low threshold vpgl pgood in from lower vo (pgood goes high) 80 85 90 % power good low hysteresis vpgl_hys pgood low hysteresis (pgood goes low) ? 5 % power good high delay td_pgh 150 us power good low delay td_pgl 1.5 us output overvoltage rising threshold ovpth+ with respect to error comparator threshold of 0.8 v 110 115 120 % overvoltage fault propagation delay ovptblk fb forced 2% above trip threshold 1.5 us output undervoltage trip threshold uvpth with respect to error comparator threshold of 0.8 v 75 80 85 % output undervoltage protection blanking time uvptblk ? 8/f sw ? s reference output internal reference voltage vref 0.7936 0.8 0.8064 v oscillator operation frequency fsw 270 300 330 khz overcurrent threshold detection total detection time t detect a short period before ss 1.26 1.92 2.21 ms ocset detection time t_ocdet (note 2) 1.09 1.47 ms 2. guaranteed by design, not tested in production.
NCP5217A http://onsemi.com 5 electrical characteristics (v in = 12 v, v cc = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol internal soft ? start soft ? start time t ss 0.9 1.1 1.3 ms voltage error amplifier dc gain gain_vea (note 2) 88 db unity gain bandwidth bw_vea (note 2) 15 mhz slew rate sr_vea comp pin to gnd = 100 pf (note 2) 2.5 v/ s fb bias current ibias_fb 0.1 a output voltage swing vmax_ea isource_ea = 2 ma 3.3 3.5 v vmin_ea isink_ea = 2 ma 0.15 0.3 differential current sense amplifier cs+ and cs ? common ? mode input signal range vcscom_max refer to agnd 3.5 v input bias current cs_iib ? 100 100 na input signal range cs_range ? 70 70 mv offset current at idrp idrp_offset (cs+) ? (cs ? ) = 0 v ? 1.0 1.0 a [(cs+) ? (cs ? )] to idrp gain idrp_gain (idrp/((cs+) ? (cs ? ))) (cs+) ? (cs ? ) = 10 mv, v(idrp) = 0.8 v t a = 25 c 0.475 0.525 0.575 a/mv t a = ? 40 c to 85 c 0.425 0.625 current ? sense bandwidth bw_cs at ? 3db to dc gain (note 2) 20 mhz maximum idrp output voltage idrp_max (cs+) ? (cs ? ) = 70 mv, isource drops to 95% of the value when v (idrp) = 0.8 v 2.5 v minimum idrp output voltage idrp_min 0 v idrp output current i_idrp ? 1.0 35 a overcurrent protection setting overcurrent threshold (octh) detection current i_ocset sourced from ocp before soft ? start, rocp = 16.7 k is connected from ocp to agnd or fb 21.6 24 26.4 a ratio of oc threshold over ocset voltage k_ocset v((cs+) ? (cs ? )) / v_ocset (note 2) 0.1 ? ocset voltage for default fixed oc threshold vocset_dft rocp 2 k is connected from ocp to agnd or fb 100 mv ocset voltage for adjustable oc threshold vocset_adj rocp = 8.3 ~ 25 k is connected from ocp to agnd or fb 200 600 mv ocset voltage for oc disable vocset_dis rocp 35 k is connected from ocp to agnd or fb 720 mv default fixed oc threshold v_octh_dft (cs+) ? (cs ? ), pin idrp/ocp is shorted to agnd or fb 35 40 45 mv adjustable oc threshold v_octh ((cs+) ? (cs ? )) (cs+) ? (cs ? ), during oc threshold, set a voltage at pin ocp vocset = 200 mv 15 20 25 mv vocset = 600 mv 52 60 68 gate drivers dh pull ? high resistance rh_dh 200 ma source current 2.5 dh pull ? low resistance rl_dh 200 ma sink current 1.5 dl pull ? high resistance rh_dl 200 ma source current 2 dl pull ? low resistance rl_dl 200 ma sink current 0.75 2. guaranteed by design, not tested in production.
NCP5217A http://onsemi.com 6 electrical characteristics (v in = 12 v, v cc = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol gate drivers dh source current isource_dh (note 2) 1 a dh sink current isink_dh (note 2) 1.7 a dl source current isource_dl (note 2) 1.3 a dl sink current isink_dl (note 2) 3.3 a dead time td_lh dl ? off to dh ? on (note 2) 20 ns td_hl dh ? off to dl ? on (note 2) 20 negative current detection threshold ncd_th swn ? pgnd, at en_skip = 5 v ? 1 mv swn source leakage iswn_sd en_skip = 0 v 1 ua internal resistor from dh to swn r_dh_swn (note 2) 100 k control section en_skip logic input voltage for disable ven_disable set as disable 0.7 1.0 1.3 v hysteresis 150 200 250 mv en_skip logic input voltage for fpwm ven_fpwm set as fccm mode 1.7 1.95 2.25 v en_skip logic input voltage for skip mode ven_skip set as skip mode 2.35 2.6 2.85 v hysteresis 100 175 250 mv en_skip source current ien_source ven_skip = 0 v 0.1 a en_skip sink current ien_sink ven_skip = 5 v 0.1 a pgood pin on resistance pgood_r i_pgood = 5 ma 100 pgood pin off current pgood_lk 1 a output discharge mode output discharge on ? resistance rdischarge en = 0 v 20 35 threshold for discharge off vth_disoff 0.2 0.3 0.4 v tre setting tre threshold detection current i_treset source from dl in the short period before soft ? start. (rtre = 47 k is connected from dl to gnd 7.2 8 8.8 a detection voltage for tre threshold selection vdl_tre_1 (default) internal tre_th is set to 300 mv rtre 75 k (note 2) 500 600 700 mv vdl_tre_2 internal tre_th is set to 500 mv rtre = 44 ~ 50 k (note 2) 300 450 vdl_tre_3 tre is disabled rtre 25 k (note 2) 0 250 tre comparator offset tre_os (note 2) 10 mv propagation delay of tre comparator td_pwm (note 2) 20 ns thermal shutdown thermal shutdown ts d (note 2) 150 c thermal shutdown hysteresis tsdhys (note 2) 25 c 2. guaranteed by design, not tested in production.
NCP5217A http://onsemi.com 7 typical operating characteristics 0.77 0.78 0.79 0.8 0.81 0.82 0.83 ? 40 ? 15 10 35 60 85 v fb v ref voltage (v) ambient temperature ( c) figure 3. v ref voltage vs ambient temperature ? 20 ? 10 0 10 ? 40 ? 15 10 35 60 85 40 30 20 ? 100 ? 50 0 50 100 150 200 ? 40 ? 15 10 35 60 85 ambient temperature ( c) v cc pin shutdown current (na) figure 4. v cc shutdown current vs ambient temperature ambient temperature ( c) 285 290 295 300 305 310 315 ? 40 ? 15 10 35 60 85 f sw switching frequency (khz) ambient temperature ( c) figure 5. switching frequency vs ambient temperature 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ? 40 ? 15 10 35 60 85 ambient temperature ( c) idrp_gain ( a/mv) figure 6. idrp gain vs ambient temperature bst pin shutdown current (na) figure 7. bst shutdown current vs ambient temperature ambient temperature ( c) 37 38 39 40 41 42 43 ? 40 ? 15 10 35 60 85 default fix oc threshold (mv) ambient temperature ( c) figure 8. default fix oc threshold vs ambient temperature
NCP5217A http://onsemi.com 8 typical operating characteristics top to bottom: en, swn, v o , pgood top to bottom: en, swn, v o , pgood figure 9. powerup sequence figure 10. powerdown sequence top to bottom: swn_slave, swm, v o top to bottom: en, swm, v o figure 11. on line mode change (ccm dcm) figure 12. on line mode change (dcm ccm) top to bottom: swn, vo, output current figure 13. typical transient
NCP5217A http://onsemi.com 9 detailed operating description general the NCP5217A synchronous step ? down power controller contains a pwm controller for wide battery/adaptor voltage range applications the NCP5217A includes power good voltage monitor, soft ? start, over current protection, under ? voltage protection, overvoltage protection and thermal shutdown. the NCP5217A features power saving function which can increase the efficiency at light load. it is ideal for battery operated systems. the ic is packaged in qfn14. control logic the internal control logic is powered by v cc . the device is controlled by an en_skip pin. the en_skip serves two functions. when voltage of en_skip is below ven_disable, it shuts down the device. when the voltage of en_skip is between ven_fpwm and ven_skip, the device is operating as force pwm mode. when voltage level of en_skip is above ven_skip, the device is operating as power saving mode. when en_skip is above ven_disable, the internal vref is activated and power ? on reset occurs which resets all the protection faults. once vref reaches its regulation voltage, an internal signal will wake up the supply under ? voltage monitor which will assert a ?good? condition. in addition, the NCP5217A continuously monitors v cc level with an undervoltage lockout (uvlo) function. forced pwm operation (fpwm mode) the device is operating as force pwm mode if en_skip voltage keeps at between ven_fpwm and ven_skip. under this mode, the low ? side gate driver signal is forced to be the complement of the high ? side gate driver signal. this mode allows reverse inductor current, in such a way that it provides more accurate voltage regulation and better (fast) transient response. during the soft ? start operation, the NCP5217A automatically runs as fpwm mode regardless of the en_skip setting at either fpwm or skip mode to make sure to have smooth power up. pulse skipping operation (skip mode) the device is operating as skip mode if en_skip voltage keeps above ven_skip. however, in medium and high load range, the controller still runs in continuous ? conduction ? mode (ccm) of which it behaves exactly same as fpwm mode. in light load range, the controller will go to skip mode which is similar to conventional constant on ? time scheme. transient response enhancement (tre) for the conventional pwm controller in ccm, the fastest response time is one switching cycle in the worst case. to further improve transient response in ccm, a transient response enhancement circuitry is implemented inside the NCP5217A. in ccm operation, the controller is continuously monitoring the comp pin output voltage of the error amplifier to detect the load transient events. the functional block diagram of tre is shown below. + r + c internal tre_th comp tre figure 14. block diagram of tre circuit once the large transient occurs, the comp signal may be large enough to exceed the threshold and then tre ?flag? signal will be asserted in a short period which is typically around one normal switching cycle. in this short period, the controller will be running at high frequency and hence has faster response. after that the controller comes back to normal switching frequency operation. we can program the internal tre threshold (tre_th). for detail please see the electrical table of ?tre setting? section. basically, the recommend internal tre threshold value is around 1.5 times of peak ? to ? peak value of the comp signal at ccm operation. the higher the internal tre_th, the lower sensitivity to load transient. the tre function can be disable by setting the rtre which is connecting to dl/tre pin to less than 25 k . for system component saving, it is usually set as default value, that is, rtre is open ( 75 k ) and internal tre_th is 300 mv typical. top to bottom swn, v o , transient signal figure 15. transient response with tre disable
NCP5217A http://onsemi.com 10 top to bottom swn, v o , transient signal figure 16. transient response with tre enable adaptive voltage positioning (avp) for applications with fast transient currents, adaptive voltage positioning can reduce peak ? to ? peak output voltage deviations due to load transients. with the use of avp, the output voltage allows to have some controlled sag when load current is applied. upon removal of the load, the output voltage returns no higher than the original level, just allowing one output transient peak to be cancelled over a load step up and release cycle. the amount of avp is adjustable. the behaviors of the v o waveforms with or without avp are depicted at figure 17. vo with avp vo without avp figure 17. adaptive voltage positioning + ? + + g i vref i drp rt rb rocp rs2 rs1 cs l dcr fb idrp/ocp cs+ cs ? comp vo figure 18. configuration for avp function the figure 18 shows how to realize the avp function. a current path is connecting to the fb pin via r ocp resistor. rocp is not actually for avp function, indeed, r ocp is used for ocp threshold value programming. the idrp/ocp pin has dual functions: ocp programming and avp. at the idrp/ocp pin, conceptually there is a current source which is modulated by current sensing amplifier. the output voltage vo with avp is: v o v o 0 i o *r ll (eq. 1) where i o is the load current, no load output voltage vo0 is set by the external divider that is v o 0 1 rt rb *v ref (eq. 2) the load line impendence r ll is given by: r ll dcr * gain_cs * rt * rs2 rs1 rs2 (eq. 3) where dcr is inductor dc resistance. gain_cs is a gain from [(cs+) ? (cs ? )] to idrp gain (at electrical table, the symbol is idrp_gain), the typical value is 0.525 a/mv. the avp function can be easily disable by shorting the rocp resistor into ground. from the equation we can see that the value of ?top? resistor rt can affect the r ll , so it is recommended to define the amount of r ll frist before defining the compensation component value. and if the user wants to fine tune the compensation network for optimizing the transient performance, it is not recommend to adjust the value of rt. otherwise, both transient performance and avp amount will be affected. the following diagram shows the typical waveform of avp. note that the rt typical value should be above 1 k . top to bottom: swn, v o , transient signal (0.5 ? 10 ? 0.5a) figure 19. typical waveform of avp
NCP5217A http://onsemi.com 11 overcurrent protection (ocp) the NCP5217A protects power system if over current event occurs. the current is continuously monitored by the differential current sensing circuit. the current limit threshold voltage vocset can be programmed by resistor rocset connecting at the idrp/ocp pin. however, fixed default vocset can be achieved if rocset is less than 2 k . if the inductor current exceeds the current threshold continuously, the top gate driver will be turned off cycle by cycle. if it happens over consecutive 16 clock cycles time (16 x 1/f sw ), the device is latched off such that top and bottom gate drivers are off. en resets or power recycle the device can exit the fault. the following diagram shows the typical behavior of ocp. top to bottom : swn, v o , pgood, i o figure 20. overcurrent protection the NCP5217A uses lossless inductor current sensing for acquiring current information. in addition, the threshold ocp voltage can be programmed to some desired value by setting the programming resistor rocp. + ? + + g i vref i drp rt rb rocp rs2 rs1 cs l dcr fb idrp/ocp cs+ cs ? comp + ? + + g i vref i drp rt rb rocp rs2 rs1 cs l dcr fb idrp/ocp cs+ cs ? comp with avp without avp vo vo figure 21. ocp configurations it should be noted that there are two configurations for rocp resistor. if adaptor v oltage position (a vp) is used, the rocp should be connected to fb pin. if avp is not used, the rocp should be connected to ground. at the idrp/ocp pin, there is a constant current(24 a typ.) flowing out during the programming stage at system start up. this is used to sense the voltage level which is developed by a resistor r ocp so as to program the overcurrent detection threshold voltage. for typical application, the v octh is set as default value (40 mv typ) by setting r ocp = 0 , or directly short the idrp/ocp pin to ground. it has the benefit of saving one component at application board. for other programming values of v octh , please refer to the electrical table of ?overcurrent protection setting? section. guidelines for selecting ocp trip component 1. choose the value of r ocp for v octh selection. (typical is 0 for v octh = 40 mv typical) 2. define the dc value of ocp trip point (i ocp_dc ) that you want. the typical value is 1.5 to 1.8 times of maximum loading current. for example, if maximum loading is 10 a, then set ocp trip point at 15 a to 18 a. 3. calculate the inductor peak current (i pk )which is estimated by the equation: i pk i ocp_dc v o *(v in v o ) 2*v in *f sw *l o (eq. 4) 4. check with inductor datasheet to find out the value of inductor dc resistance dcr, then calculate the rs1, rs2 dividing factor k based on the equation: k v octh i pk * dcr (eq. 5) 5. select cs value between 100 nf to 200 nf. typically, 100 nf will be used. 6. calculate rs1 value by the equation: rs1 l k * dcr * cs (eq. 6) 7. calculate rs2 value by the equation: rs2 k*rs1 1 k (eq. 7) 8. hence, all the current sense components rs1, rs2, cs have been found for target i ocp_dc . 9. if rs2 is not used (open), set k = 1, at that moment, the i pk will be restricted by: i pk v octh dcr (eq. 8) overvoltage protection (ovp) when v fb voltage is above 1 15% (typical) of the nominal v fb voltage for over 1.5 s blanking time, an ov fault is set. at that moment, the top gate drive is turned off and the bottom gate drive is turned on until the v fb below lower under voltage (uv) threshold and bottom gate drive is
NCP5217A http://onsemi.com 12 turned on again whenever v fb goes above upper uv threshold. en resets or power recycle the device can exit the fault. the following diagram shows the typical waveform when ovp event occurs. figure 22. overvoltage protection top to bottom : swn, dl, v o , pgood undervoltage protection (uvp) an uvp circuit monitors the v fb voltage to detect under voltage event. the undervoltage limit is 80% of the nominal v fb voltage. if the v fb voltage is below this threshold over consecutive 8 clock cycles, an uv fault is set and the device is latched off such that both top and bottom gate drives are off. en resets or power recycle the device can exit the fault. figure 23. undervoltage protection top to bottom : swn, v o , pgood thermal shutdown the ic will shutdown if the die temperature exceeds 150 c. the ic restarts operation only after the junction temperature drops below 125 c. v5 vin vout pgood bst dh swn idrp/ocp vcc pgnd agnd pgood cs ? /vo comp fb dl/treset en_skip cs+ 6 NCP5217A 5 4 3 2 7 1 14 8 9 10 11 12 13 +5v +5v en_skip vin_gn d pgnd pgnd r3 r4 r5 j1 m5 r1 r11 r2 c2 r6 c1 c3 c4 r7 r8 r9 comp j100 c5 d1 r12 r13 r10 c20 r14 m1 m2 r15 c6 r16 m3 m4 r18 r17 c10 r21 d2 l1 r19 r20 c7 c8 c9 c11 agnd c14 c15 c17 c18 bnc1 j2 d3 sw1 1 2 3 off = skip mode 1 ? 2 = fccm mode 3 ? 2 = disable 1 2 3 1 ? 2 = ocp only 3 ? 2 = ocp + avp j100 default = open j1 default = close led1 led2 u1 agnd pgnd pgnd figure 24. demo board schematic
NCP5217A http://onsemi.com 13 demo board bill of material bom (see next tables for compensation network and power stage) designator qty description value footprint manufacturer manufacturer p/n u1 1 single synchronous stepdown controller ? qfn14 (special) on semiconductor ncp5217mnr2g r1 1 chip resistor, 5% 75k 0603 panasonic erj3geyj753v r2 1 chip resistor, 5% 10k 0603 panasonic erj3geyj103v r3, r4 2 chip resistor, 5% 1k 0603 panasonic erj3geyj102v r5 1 chip resistor, 5% 100k 0603 panasonic erj3geyj104v r10 1 chip resistor, 5% 5.6 0603 panasonic erj3geyj5r6v r11 1 chip resistor, 5% 20k 0603 panasonic erj3geyj203v r12 1 chip resistor, 5% 5.6 0603 panasonic erj3geyj5r6v r13, r14, r15, r17 4 chip resistor, 5% 0 0603 panasonic erj3geyjr00v r16, r18, r21, 3 ? dnp ? ? ? c1 1 mlcc chip capacitor, 10% temp char: x7r, rate v = 50 v 100 nf 0603 panasonic ecj1vb1e104k c5, c6 2 mlcc chip capacitor, 20% temp char: x5r, rate v=25v 1 f 0805 panasonic ecj2fb1e105m c7,c8,c9, c11 4 mlcc chip capacitor, 20% temp char: x5r, rate v = 25 v 4.7 f 0805 panasonic ecj2fb1e475m c10, c13, c17, c18 4 ? dnp ? ? ? c20 1 mlcc chip capacitor, 20% temp char: x7r, rate v = 50 v 0.1 f 0603 panasonic ecj1vb1e104m d1 1 30v schottky diode vf=0.35v @ 10ma ? sot ? 23 on semiconductor bat54lt1 d2, d3 1 ? dnp ? ? ? m5 1 power mosfet 50 v, 200 ma single n ? channel ? sot ? 23 on semiconductor bss138l led1 1 surface mount led (green) ? 0805 lumex sml ? lx0805gc ? tr led2 1 surface mount led (red) ? 0805 lumex sml ? lx0805ic ? tr j1, j100, comp, en_skip, pgood, agnd 6 pin header single row ? pitch=2.54 mm betamax 2211s ? 40g ? f1 v5, vin, vin_gnd, pgnd, pgnd, pgnd, vout 7 terminal pin ? f = 1.74 mm harwin h2121 ? 01 bnc1 1 smb smt straight socket ? 5.1 x 5.1 mm tyco electronics rs stock# 420 ? 5401 sw1 1 2p on ? off ? on toggle switch ? 3 pins, 2.54 mm pitch c & k rs stock# 249 ? 2984 manufacturer # 7203sycqe
NCP5217A http://onsemi.com 14 demo board bill of material (v o = 1.1 v, i o = 15 a) item component value tol footprint manufacturer manufacturer p/n compensation network r6 100k 1% 0603 panasonic erj3ekf1003v r7 560 1% 0603 panasonic erj3ekf5600v r8 3k 1% 0603 panasonic erj3ekf3001v r9 8k 1% 0603 panasonic erj3ekf8001v c2 470 pf 10% 0603 panasonic ecj1vc1h471k c3 15 pf 10% 0603 panasonic ecj1vc1h150k c4 1.2 nf 10% 0603 panasonic ecj1vb1h122k power stage & current sense m1, m2 ? ? soic8 ? fl on semiconductor ntmfs4821n m3, m4 ? ? soic8 ? fl on semiconductor ntmfs4847n l1 1 h 20% 10x11.5mm cyntec pcmc104t ? 1r0mn r19 6.2k 1% 0603 panasonic erj3ekf6201v r20 9.1k 1% 0603 panasonic erj3ekf9101v c14, c15 330 f 6 m 20% 7343 panasonic eefsx0d331xr sanyo 2tplf330m6 demo board bill of material (v o = 1.5 v, i o = 8 a) item component value tol footprint manufacturer manufacturer p/n compensation network r6 82k 1% 0603 panasonic erj3ekf8202v r7 1k 1% 0603 panasonic erj3ekf1001v r8 5k 1% 0603 panasonic erj3ekf5001v r9 5.71k 1% 0603 panasonic erj3ekf5711v c2 270 pf 10% 0603 panasonic ecj1vc1h271k c3 15 pf 10% 0603 panasonic ecj1vc1h150k c4 560 pf 10% 0603 panasonic ecj1vb1h561k power stage & current sense m1, m3 ? ? so8 on semiconductor ntms4705n m2, m4 dnp ? ? ? ? l1 1 h 20% 10x11.5mm cyntec pcmc104t ? 1r0mn r19 4.3k 1% 0603 panasonic erj3ekf4301v r20 dnp ? ? ? ? c14, c15 220 f 12 m 20% 7343 panasonic eefud0d221xr sanyo 2r5tpl220mc
NCP5217A http://onsemi.com 15 demo board bill of material (v o = 1.8 v, i o = 8 a) item component value tol footprint manufacturer manufacturer p/n compensation network r6 150k 1% 0603 panasonic erj3ekf1503v r7 1k 1% 0603 panasonic erj3ekf1001v r8 5k 1% 0603 panasonic erj3ekf5001v r9 4k 1% 0603 panasonic erj3ekf4001v c2 220pf 10% 0603 panasonic ecj1vc1h221k c3 18pf 10% 0603 panasonic ecj1vc1h180k c4 560pf 10% 0603 panasonic ecj1vb1h561k power stage & current sense m1, m3 ? ? so8 on semi ntms4705n m2, m4 dnp ? ? ? ? l1 1.2uh 20% 10x11.5mm toko fda1254 ? 1r2m=p3 r19 4.3k 1% 0603 panasonic erj3ekf4301v r20 dnp ? ? ? ? c14, c15 220uf 12m 20% 7343 panasonic eefud0d221xr sanyo 2r5tpl220mc
NCP5217A http://onsemi.com 16 package dimensions qfn14 3.5x3.5, 0.5p case 485al ? 01 issue o 14x seating plane l d e 0.15 c a a1 e d2 e2 b 7 9 14 1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c note 4 14x 0.10 c 0.05 c a b note 3 k 14x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.50 bsc d2 1.90 2.15 e 3.50 bsc e2 1.90 2.15 e 0.50 bsc k 0.20 ??? l 0.30 0.50 detail a e2 1.50 bsc 2x 2x l detail a optional pin construction *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.12 3.80 1.50 pitch 0.50 0.36 14x dimensions: millimeters 2 e2 2x 2x 0.63 14x pitch l1 detail a 0.00 0.03 detail b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5217A/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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